Before we begin In this part we’ll take a look at RAM, program counter and instruction fetch concepts. But before we go further, and since the files are getting too large to post here, we need to grab them from a git repository. Please head over to https://github.com/ecilasun/nekoichiarticle and use the following command to pull […]

Welcome to part 5 of the series. In this one we’ll be looking at making a state machine, and run a simulation of it to make sure it works. RISC-V CPU States The RISC-V CPU has a very interesting model which makes implementing it quite easy. Memory access is limited to load and store instructions, […]

Welcome to part 4 of the series. Before we continue, if you haven’t done so, I recommend going back to the first part and syncing up and installing the tools required for the rest of the series. Getting started: Vivado and Board Files Even though you have access to the final live project files on […]

Now it’s time for us to start looking at ways that will allow us to implement our hardware in SystemVerilog. If you’re unfamiliar with hardware definition languages, I can suggest a quick detour and skim through the Wikipedia entry on the subject. In summary, this is the language we’ll be using to describe our hardware, […]

In this part of the series we’ll take a very quick look at the RISC-V ISA, especially the bits that interest us. Most of the ISA can be safely skipped as it’s organized into a series of ‘feature levels’, out of which only one is mandatory to implement (namely the base integer set, I) If […]

During these last few months I’ve been working on creating a small system with a 32bit RISC-V CPU (conforming to rv32imf model), alongside with a custom GPU. The purpose is to have a system that I can write some small games on and use as a teaching model. I also wanted to have GDB support […]