New design

I’ve been working on something different for a while now, and I think I have a system that is about 80% usable.

The new system depends on a fairly reasonably priced core board that carries a Xilinx A7-200T part, made by QMTECH. I’ve built an expansion board around it to add some required features which are listed below.

  • A micro SD Card reader
  • A USB-A port and controller for HID device connection
  • An 8 channel analog-digital converter
  • A digital-analog converter for audio output
  • HDMI port (provides DVI video output)
  • Stereo audio output jack
  • A USB-C port and controller for host device USB access
  • Debug UART port
  • Reset button and 4 debug LEDs

In addition to the hardware, I’ve also been working on a micro OS that supports most commonly used syscalls, so that one can use off-the shelf RISC-V and the provided SDK to build applications without the need for custom linker scripts.

The OS currently supports one executable loaded form SD card and a low priority OS task to run simultaneously, and responds to hardware interrupts such as SD card insert/eject, timers etc. The memory allocation facilities are not impressive at this point (no map() due to missing MMU) but it does provide the brk syscall so loaded apps can request memory from OS via malloc() and free using free(). I’ve run C++14 apps without much concern so I suppose most facilities work at this point including file access.

The SoC currently carries these devices implemented on the FPGA fabric:

  • A simple block DMA device that can move blocks at 16 byte aligned addresses in increments of 16 bytes (single transfer is limited to 4096 bytes)
  • A simple GPU that provides either 320×240 or 640×480 indexed color output with user defined framebuffer addresses, burst reads from DDR3 to output video data
  • A raw audio output unit with 44/22/11 KHz sample rate support
  • An OPL2 compatible device (JTOPL by Jose Tejada Gomez , this is awesome work!)
  • SPI interfaces to SD card and USB-C device (MAX3420E)
  • An UART (device is fixed at 115200 8n1)
  • Some Xilinx cores to control the onboard DDR3 memory
  • A RISC-V CPU (current feature set is rv32imcZcsr, therefore it has hardware DIV/MUL/REM and supports compressed instructions and the base instruction set, as well as most of the 4096 CSRs)
  • A simple round-robin arbiter to shuffle memory access between 6 devices

More devices and perhaps an extra CPU is to follow, given I have time and space for it.

Bugs and TODOs:

  • SD card writes do not function properly, could be due to the ff library used
  • Soft-reset button needs more stability (longer debounce period)
  • USB-C works without the INT pin, enabling INT pin fires hardware interrupt only once, investigating this
  • GDB server sort of works, but needs more work to be robust. Will probably lift existing gdbserver core instead of custom one to ensure it’s implemented right
  • No MMU, therefore no virtual memory support, which prevents me from running more than the OS plus one application. This is also in the works.
  • Analog input channels work, but they have some noise. Might need some capacitors on the board
  • There is no output volume control or mixer control between the OPL2 and the raw audio. Will address that later

As soon as everything is in a usable state, I’ll post the board schematics, OS code, samples modified to run on this SoC (of course, DOOM! included), documentation and the FPGA verilog project.

It’s a big project, so please stay tuned until my next update.